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features ? hcmos/lsttl/ttl performance compatible ? 1000 v/ s minimum common mode rejection (cmr) at v cm = 50 v (hcpl-261a family) and 15 kv/ s minimum cmr at v cm = 1000 v (hcpl-261n family) ? high speed: 10 mbd typical ? ac and dc performance specifed over industrial temperature range -40c to +85c ? available in 8 pin dip, soic-8 packages ? safety approval: C ul recognized per ul1577 3750 v rms for 1 minute and 5000 v rms for 1 minute (option 020) C csa approved C iec/en/din en 60747-5-5 approved applications ? low input current (3.0 ma) hcmos compatible version of 6n137 optocoupler ? isolated line receiver ? simplex/multiplex data transmission ? computer-peripheral interface ? digital isolation for a/d, d/a conversion ? switching power supplies ? instrumentation input/output isolation ? ground loop elimination ? pulse transformer replacement hcpl-261a, hcpl-061a, hcpl-263a, hcpl-063a hcpl-261n, hcpl-061n, hcpl-263n, hcpl-063n hcmos compatible, high cmr, 10 mbd optocouplers data sheet the connection of a 0.1 f bypass capacitor between pins 5 and 8 is required. description the hcpl-261a family of optically coupled gates shown on this data sheet provide all the benefts of the in - dustry standard 6n137 family with the added beneft of hcmos compatible input cur rent. this allows direct interface to all common circuit topologies without additional led bufer or drive components. the al - gaas led used allows lower drive currents and reduc - es degradation by using the latest led tech nol ogy. on the single channel parts, an enable output allows the de - tector to be strobed. the output of the detector ic is an open collector schottky-clamped transistor. the internal shield provides a mini mum common mode transient im - munity of 1000 v/ s for the hcpl-261a family and 15000 v/ s for the hcpl-261n family. functional diagram caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product 1 2 3 4 8 7 6 5 cathode anode gnd v v cc o 1 2 3 4 8 7 6 5 anode 2 cathode 2 cathode 1 anode 1 gnd v v cc o2 v e v o1 hcpl-261a/261n hcpl-061a/061n hcpl-263a/263n hcpl-063a/063n nc nc shield shield led on off on off on off enable h h l l nc nc output l h h h l h truth table (positive logic) led on off output l h truth table (positive logic)
2 selection guide widebody minimum cmr 8-pin dip (300 mil) small-outline so-8 (400 mil) hermetic on- single dual single dual single single and dv/dt v cm current output channel channel channel channel channel dual channel (v/s) (v) (ma) enable package package package package package packages na na 5 yes 6n137 [1] hcpl-0600 [1] hcnw137 [1] no hcpl-2630 [1] hcpl-0630 [1] 5,000 50 yes hcpl-2601 [1] hcpl-0601 [1] hcnw2601 [1] no hcpl-2631 [1] hcpl-0631 [1] 10,000 1,000 yes hcpl-2611 [1] hcpl-0611 [1] hcnw2611 [1] no hcpl-4661 [1] hcpl-0661 [1] 1,000 50 yes hcpl-2602 [1] 3,500 300 yes hcpl-2612 [1] 1,000 50 3 yes hcpl-261a hcpl-061a no hcpl-263a hcpl-063a 1,000 [2] 1,000 yes hcpl-261n hcpl-061n no hcpl-263n hcpl-063n 1,000 50 12.5 [3] hcpl-193x [1] hcpl-56xx [1] hcpl-66xx [1] note s: 1. technical data are on separate avago publications. 2. 15 kv/ s with v cm = 1 kv can be achieved using avago application circuit. 3. enable is available for single channel products only, except for hcpl-193x devices. input schematic shield 8 6 5 2+ 3 v f use of a 0.1 f bypass capacitor connected between pins 5 and 8 is recommended (see note 16). ? i f i cc v cc v o gnd i o v e i e 7 hcpl-261a/261n hcpl-061a/061n shield 8 7 + 2 v f1 ? i f1 i cc v cc v o1 i o1 1 shield 6 5 ? 4 v f2 + i f2 v o2 gnd i o2 3 hcpl-263a/263n hcpl-063a/063n
3 ordering information hcpl-xxxx is ul recognized with 3750 v rms for 1 minute per ul1577. part number option package surface mount gull wing tape & reel ul 5000 vrms/1 minute rating iec/en/din en 60747-5-5 quantity rohs compliant non rohs compliant hcpl-261a -000e no option 300mil dip-8 50 per tube -300e #300 x x 50 per tube -500e #500 x x x 1000 per reel -020e #020 x 50 per tube -320e -320 x x x 50 per tube -520e -520 x x x x 1000 per reel -060e #060 x 50 per tube -560e #560 x x x x 1000 per reel hcpl- 261n -000e no option 300mil dip-8 50 per tube -300e #300 x x 50 per tube -500e #500 x x x 1000 per reel -020e #020 x 50 per tube -320e #320 x x x 50 per tube -520e -520 x x x x 1000 per reel -060e #060 x 50 per tube -360e #360 x x x 50 per tube -560e - x x x x 1000 per reel hcpl-263a -000e no option 300mil dip-8 50 per tube -300e #300 x x 50 per tube -500e #500 x x x 1000 per reel -020e #020 x 50 per tube -320e #320 x x x 50 per tube -520e -520 x x x x 1000 per reel hcpl- 263n -000e no option 300mil dip-8 50 per tube -300e #300 x x 50 per tube -500e #500 x x x 1000 per reel -020e #020 x 50 per tube -320e #320 x x x 50 per tube -520e #520 x x x x 1000 per reel hcpl-061a hcpl- 061n -000e no option so-8 x 100 per tube -500e #500 x x 1500 per reel -060e #060 x x 100 per tube -560e #560 x x x 1500 per reel hcpl-063a hcpl- 063n -000e no option so-8 x 100 per tube -500e #500 x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. combination of option 020 and option 060 is not available. example 1: hcpl-261a-560e to order product of 300mil dip gull wing surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval in rohs compliant. example 2: hcpl-263n to order product of 300mil dip package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe.
4 hcpl-261a/261n/263a/263n outline drawing pin location (for reference only) figure 2. gull wing surface mount option #300. figure 1. 8-pin dual in-line package device outline drawing. 9.40 (0.370) 9.90 (0.390) pin one 1.78 (0.070) max. a xxxxz yyww option code* date code 0.76 (0.030) 1.40 (0.056) 2.28 (0.090) 2.80 (0.110) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. 6.10 (0.240) 6.60 (0.260) 0.20 (0.008) 0.33 (0.013) 5 typ. 7.36 (0.290) 7.88 (0.310) dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 1.19 (0.047) max. type number * marking code letter for option numbers. "l" = option 020 "v" = option 060 option numbers 300 and 500 not marked. note: floating lead protrusion is 0.25 mm (10 mils) max. 3.56 0.13 (0.140 0.005) 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.02 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.540 (0.100) bsc dimensions in millimeters (inches). tolerances (unless otherwise specified): lead coplanarity maximum: 0.102 (0.004) note: floating lead protrusion is 0.25 mm (10 mils) max. xx.xx = 0.01 xx.xxx = 0.005 0.20 (0.008) 0.33 (0.013)
5 hcpl-061a/061n/063a/063n outline drawing figure 3. 8-pin small outline package device drawing. solder refow profle recommended refow condition as per jedec standard, j-std-020 (latest revision). non-halide flux should be used. regulatory information the hcpl-261a and hcpl-261n families have been approved by the following organizations: ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca 88324. iec/en/din en 60747-5-5 xxx yww 8 7 6 5 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc * 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. * total package length (inclusive of mold flash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. 0.203 0.102 (0.008 0.004) 7 note: floating lead protrusion is 0.15 mm (6 mils) max. 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation
6 insulation and safety related specifcations 8-pin dip (300 mil) so-8 parameter symbol value value units conditions minimum external air l(101) 7.1 4.9 mm measured from input terminals to gap (external output terminals, shortest distance clearance) through air. minimum external l(102) 7.4 4.8 mm measured from input terminals to tracking (external output terminals, shortest distance creepage) path along body. minimum internal plastic 0.08 0.08 mm through insulation distance, conductor gap (internal clearance) to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. tracking resistance cti 200 200 volts din iec 112/ vde 0303 part 1 (comparative tracking index) isolation group iiia iiia material group (din vde 0110, 1/89, table 1) option 300 C surface mount classifcation is class a in accordance with cecc 00802. iec/en/din en 60747-5-5 insulation characteristics* description symbol pdip option 060 so-8 option 060 unit installation classifcation per din vde 0110, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 600 v rms i C iv i C iv i C iii i C iv i C iv i C iii climatic classifcation 40/85/21 40/85/21 pollution degree (din vde 0110/39) 2 2 maximum working insulation voltage v iorm 630 567 v peak input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m =1 sec, partial discharge < 5 pc v pr 1181 1063 v peak input to output test voltage, method a* v iorm x 1.6 = v pr , type and sample test, t m =10 sec, partial discharge < 5 pc v pr 1008 907 v peak highest allowable overvoltage (transient overvoltage t ini = 60 sec) v iotm 6000 6000 v peak safety-limiting values C maximum values allowed in the event of a failure case temperature t s 175 150 c input current i s, input 230 150 ma output power p s, output 600 600 mw insulation resistance at t s , v io = 500 v r s 10 9 10 9 w * refer to the front of the optocoupler section of the current catalog, under product safety regulations section iec/en/din en 60747-5-5, for a detailed description.
7 absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 +85 c average input current i f(avg) 10 ma 1 reverse input voltage v r 3 volts supply voltage v cc -0.5 7 volts 2 enable input voltage v e -0.5 5.5 volts output collector current (each channel) i o 50 ma output power dissipation (each channel) p o 60 mw 3 output voltage (each channel) v o -0.5 7 volts lead solder temperature 260c for 10 s, 1.6 mm below seating plane (through hole parts only) solder refow temperature profle see package outline drawings section (surface mount parts only) recommended operating conditions parameter symbol min. max. units input voltage, low level v fl -3 0.8 v input current, high level i fh 3.0 10 ma power supply voltage v cc 4.5 5.5 volts high level enable voltage v eh 2.0 v cc volts low level enable voltage v el 0 0.8 volts fan out (at r l = 1 kf) n 5 ttl loads output pull-up resistor r l 330 4k f operating temperature t a -40 85 c
8 electrical specifcations over recommended operating temperature (t a = - 40c to +85c) unless otherwise specifed. parameter symbol min. typ.* max. units test conditions fig. note high level output i oh 3.1 100 a v cc = 5.5 v, v o = 5.5 v, 4 18 current v f = 0.8 v, v e = 2.0 v low level output v ol 0.4 0.6 v v cc = 5.5 v, i ol = 13 ma 5, 8 4, 18 voltage (sinking), i f = 3.0 ma, v e = 2.0 v high level supply i cch 7 10 ma v e = 0.5 v** v cc = 5.5 v 4 9 15 dual channel products*** low level supply i ccl 8 13 ma v e = 0.5 v** v cc = 5.5 v 12 21 dual channel products*** high level enable i eh -0.6 -1.6 ma v cc = 5.5 v, v e = 2.0 v current** low level enable i el -0.9 -1.6 ma v cc = 5.5 v, v e = 0.5 v current** input forward v f 1.0 1.3 1.6 v i f = 4 ma 6 4 voltage temperature co- ?v f /?t a -1.25 mv/c i f = 4 ma 4 efcient of forward voltage input reverse bv r 3 5 v i r = 100 a 4 breakdown voltage input capacitance c in 60 pf f = 1 mhz, v f = 0 v *all typical values at t a = 25c, v cc = 5 v **single channel products only (hcpl-261a/261n/061a/061n) ***dual channel products only (hcpl-263a/263n/063a/063n) i f = 0 ma i f = 3.0 ma current current
9 switching specifcations over recommended operating temperature (t a = -40c to +85c) unless otherwise specifed. parameter symbol min. typ.* max. units test conditions fig. note input current threshold i thl 1.5 3.0 ma v cc = 5.5 v, v o = 0.6 v, 7, 10 18 high to low i o >13 ma (sinking) propagation delay t plh 52 100 ns i f = 3.5 ma 9, 11, 4, 9, time to high output v cc = 5.0 v, 12 18 level v e = open, propagation delay t phl 53 100 ns 9, 11, 4, 10, time to low output 12 18 level pulse width distortion pwd 11 45 ns 9, 13 17, 18 |t phl - t plh | propagation delay skew t psk 60 ns 24 11, 18 output rise time t r 42 ns 9, 14 4, 18 output fall time t f 12 ns 9, 14 4, 18 propagation delay t ehl 19 ns i f = 3.5 ma 15, 12 time of enable v cc = 5.0 v, 16 from v eh to v el v el = 0 v, v eh = 3 v, propagation delay t elh 30 ns 15, 12 time of enable 16 from v el to v eh *all typical values at t a = 25c, v cc = 5 v. c l = 15 pf, r l = 350 f c l = 15 pf, r l = 350 f common mode transient immunity specifcations, all values at t a = 25c parameter device symbol min. typ. max. units test conditions fig. note output high hcpl-261a |cm h | 1 5 kv/s v cm = 50 v v cc = 5.0 v, 17 4, 13, level common hcpl-061a r l = 350 f, 15, 18 mode transient hcpl-263a i f = 0 ma, immunity hcpl-063a t a = 25c hcpl-261n 1 5 kv/s v cm = 1000 v hcpl-061n hcpl-263n 15 25 kv/s using avago 20 4, 13, hcpl-063n app circuit 15 output low hcpl-261a |cm l | 1 5 kv/s v cm = 50 v v cc = 5.0 v, 17 4, 14, level common hcpl-061a r l = 350 f, 15, 18 mode transient hcpl-263a i f = 3.5 ma, immunity hcpl-063a v o(max) = 0.8 v hcpl-261n 1 5 kv/s v cm = 1000 v hcpl-061n hcpl-263n 15 25 kv/s using avago 20 4, 14, hcpl-063n app circuit 15 v o(min) = 2 v t a = 25c
10 package characteristics all typicals at t a = 25c parameter sym. package* min. typ. max. units test conditions fig. note input-output v iso 3750 v rms rh 50%, 5, 6 momentary with- t = 1 min., stand voltage** t a = 25c input-output r i-o 10 12 f v i-o = 500 vdc 4, 8 resistance input-output c i-o 0.6 pf f = 1 mhz, 4, 8 capacitance t a = 25c input-input i i-i dual channel 0.005 a rh 45%, 19 insulation t = 5 s, leakage current v i-i = 500 v resistance r i-i dual channel 10 11 f 19 (input-input) capacitance c i-i dual 8-pin dip 0.03 pf f = 1 mhz 19 dual so-8 0.25 *ratings apply to all devices except otherwise noted in the package column. **the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to the iec/en/din en 60747-5-5 insulation characteristics table (if applicable), your equip - ment level safety specifcation or avago application note 1074 entitled optocoupler input-output endurance voltage. ?for 8-pin dip package devices (hcpl-261a/261n/263a/263n) only. (input-input) opt 020? 5000 5, 7 notes: 1. peaking circuits may be used which produce transient input currents up to 30 ma, 50 ns maximum pulse width, provided the average cur - rent does not exceed 10 ma. 2. 1 minute maximum. 3. derate linearly above 80 c free-air temperature at a rate of 2.7 mw/c for the soic-8 package. 4. each channel. 5. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 6. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detec - tion current limit, i i-o 5 a). this test is performed before the 100% production test for partial discharge (method b) shown in the iec/en/ din en 60747-5-5 insulation characteristics table, if applicable. 7. in accordance with ul1577, each optocoupler is proof tested by applying an insulation test voltage 6000 v rms for 1 second (leakage detec - tion current limit, i i-o 5 a). 8. measured between the led anode and cathode shorted together and pins 5 through 8 shorted together. 9. the t plh propagation delay is measured from the 1.75 ma point on the falling edge of the input pulse to the 1.5 v point on the rising edge of the output pulse. 10. the t phl propagation delay is measured from the 1.75 ma point on the rising edge of the input pulse to the 1.5 v point on the falling edge of the output pulse. 11. propagation delay skew (t psk ) is equal to the worst case diference in t plh and/or t phl that will be seen between any two units under the same test conditions and operating temperature. 12. single channel products only (hcpl-261a/261n/061a/061n). 13. common mode transient immunity in a logic high level is the maximum tolerable |dv cm /dt| of the common mode pulse, v cm , to assure that the output will remain in a logic high state (i.e., v o > 2.0 v). 14. common mode transient immunity in a logic low level is the maximum tolerable |dv cm /dt| of the common mode pulse, v cm , to assure that the output will remain in a logic low state (i.e., v o < 0.8 v). 15. for sinusoidal voltages (|dv cm /dt|)max = f cm v cm(p-p) . 16. bypassing of the power supply line is required with a 0.1 f ceramic disc capacitor adjacent to each optocoup ler as shown in figure 19. total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. 17. pulse width distortion (pwd) is defned as the diference between t plh and t phl for any given device. 18. no external pull up is required for a high logic state on the enable input of a single channel product. if the v e pin is not used, tying v e to v cc will result in improved cmr performance. 19. measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. for dual channel parts only.
11 i oh ? high level output current ? a -60 0 t a ? temperature ? c 100 10 15 -20 5 20 v cc = 5.5 v v o = 5.5 v v e = 2 v v f = 0.8 v 60 -40 0 40 80 i ol ? low level output current ? ma -60 0 t a ? temperature ? c 100 60 80 -20 20 20 v cc = 5 v v e = 2 v v ol = 0.6 v i f = 3.5 ma 60 -40 0 40 80 40 i f ? input forward current ? ma 1.0 0.01 v f ? forward voltage ? v 1.5 10.0 100.0 1.2 0.1 1.4 1.1 1.3 1.0 t a = 85 c t a = 40 c t a = 25 c i f + ? v f v o ? output voltage ? v 0 0 i f ? forward input current ? ma 2.0 4.0 5.0 1.0 2.0 0.5 1.5 3.0 1.0 r l = 4 kw r l = 350 r l = 1 k v ol ? low level output voltage ? v -60 0.2 t a ? temperature ? c 100 0.5 0.6 -20 0.3 20 60 -40 0 40 80 0.4 v cc = 5.5 v v e = 2 v i f = 3.0 ma i o = 16 ma i o = 12.8 ma i o = 9.6 ma i o = 6.4 ma figure 9. test circuit for t phl and t plh . figure 4. typical high level output current vs. temperature. figure 6. typical diode input forward current characteristic. figure 5. low level output current vs. temper - ature. figure 7. typical output voltage vs. forward input current. figure 8. typical low level output voltage vs. temperature. output v monitoring node o 1.5 v t phl t plh i f input o v output i = 3.5 ma f i = 1.75 ma f +5 v 7 5 6 8 2 3 4 1 pulse gen. z = 50 t = t = 5 ns o f i f l r r m cc v 0.1 f bypass *c l *c is approximately 15 pf which includes probe and stray wiring capacitance. l gnd input monitoring node r hcpl-261a/261n 90% 90% 10% 10% t rise t fall v oh v ol
12 i th ? input threshold current ? ma -60 0 t a ? temperature ? c 100 1.5 2.0 -20 0.5 20 60 -40 0 40 80 1.0 v cc = 5 v v o = 0.6 v r l = 350 r l = 1 k r l = 4 k t p ? propagation delay ? ns -60 0 t a ? temperature ? c 100 100 120 -20 40 20 60 -40 0 40 80 60 80 20 tplh r l = 4 k tplh r l = 1 k tplh r l = 350 k tphl r l = 350 , 1 k, 4 k v cc = 5 v i f = 3.5 ma t p ? propagation delay ? ns 0 0 i f ? pulse input current ? ma 12 100 120 2 40 6 8 4 10 60 80 20 tplh r l = 4 k v cc = 5 v t a = 25 c tplh r l = 1 k tphl r l = 350 , 1 k, 4 k tplh r l = 350 t r , t f ? rise, fall time ? ns -60 0 t a ? temperature ? c 100 140 160 -20 40 20 60 -40 0 40 80 60 120 20 v cc = 5 v i f = 3.5 ma r l = 4 k r l = 1 k r l = 350 , 1 k, 4 k t rise t fall r l = 350 pwd ? ns -60 0 t a ? temperature ? c 100 50 60 -20 20 20 60 -40 0 40 80 30 40 10 r l = 1 k r l = 350 v cc = 5 v i f = 3.5 ma r l = 4 k figure 10. typical input threshold current vs. temperature. figure 13. typical pulse width distortion vs. temperature. figure 11. typical propagation delay vs. tem - perature. figure 12. typical propagation delay vs. pulse input current. figure 14. typical rise and fall time vs. temperature.
13 output v monitoring node o 1.5 v t ehl t elh v e input o v output 3.0 v 1.5 v +5 v 7 5 6 8 2 3 4 1 pulse gen. z = 50 t = t = 5 ns o f i f l r cc v 0.1 f bypass *c l *c is approximately 15 pf which includes probe and stray wiring capacitance. l gnd r 3.5 ma input v e monitoring node hcpl-261a/261n t e ? enable propagation delay ? ns -60 0 t a ? temperature ? c 100 90 120 -20 30 20 60 -40 0 40 80 60 v cc = 5 v v eh = 3 v v el = 0 v i f = 3.5 ma t elh , r l = 4 k t elh , r l = 1 k t ehl , r l = 350 , 1k , 4 k t elh , r l = 350 v o 0.5 v o v (min.) 5 v 0 v switch at a: i = 0 ma f switch at b: i = 3.5 ma f cm v h cm cm l o v (max.) cm v (peak) v o +5 v 7 5 6 8 2 3 4 1 cc v 0.1 f bypass gnd output v monitoring node o pulse gen. z = 50 o + _ 350 i f b a v ff cm v hcpl-261a/261n output power ? p s , input current ? i s 0 0 t s ? case temperature ? c 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 p s (mw) i s (ma) hcpl-261a/261n option 060 only 175 figure 15. test circuit for t ehl and t elh . figure 17. test circuit for common mode transient immunity and typical waveforms. figure 16. typical enable propaga tion delay vs. temperature. hcpl-261a/-261n/-061a/-061n only. figure 18. thermal derating curve, dependence of safety limiting value with case temperature per iec/en/din en 60747-5-5.
14 figure 20. recommended drive circuit for hcpl-261a/-261n families for high-cmr (similar for hcpl-263a/-263n). application information common-mode rejection for hcpl- 261a/hcpl-261n families: figure 20 shows the recom mended drive circuit for the hcpl-261n/- 261a for optimal common-mode rejection performance. two main points to note are: 1. the enable pin is tied to v cc rather than foating (this applies to single-channel parts only). 2. two led-current setting resistors are used instead of one. this is to balance i led variation during common-mode transients. if the enable pin is left foating, it is possible for common-mode tran - sients to couple to the enable pin, resulting in common-mode failure. this failure mechanism only occurs when the led is on and the output is in the low state. it is identifed as occurring when the transient output voltage rises above 0.8 v. therefore, the enable pin should be connected to either v cc or logic-level high for best common-mode performance with the output low (cmr l ). this failure mechanism is only present in single-channel parts (hcpl-261n, -261a, - 061n, -061a) which have the enable function. also, common-mode transients can capacitively couple from the led an - ode (or cathode) to the output-side ground causing current to be shunt - ed away from the led (which can be bad if the led is on) or conversely cause current to be injected into the led (bad if the led is meant to be of ). figure 21 shows the parasitic capacitances which exists between led anode/cathode and output ground (c la and c lc ). also shown in figure 21 on the input side is an ac- equivalent circuit. *higher cmr may be obtainable by connecting pins 1, 4 to input ground (gnd1). single channel products figure 19. recommended printed circuit board layout. dual channel products enable (if used) gnd bus (back) v bus (front) cc n.c. n.c. n.c. n.c. output 1 output 2 enable (if used) 0.1f 0.1f 10 mm max. (see note 16) gnd bus (back) v bus (front) cc output 1 output 2 0.1f 10 mm max. (see note 16) 0.01 f 350 74ls04 or any totem-pole output logic gate v o v cc+ 8 7 6 1 3 shield 5 2 4 hcpl-261a/261n gnd gnd2 357 (max.) v cc 357 (max.) * * * higher cmr may be obtainable by connecting pins 1, 4 to input ground (gnd1). gnd1
15 figure 22. ttl interface circuit for the hcpl-261a/-261n families. table 1 indicates the directions of i lp and i ln fow depend - ing on the direction of the common-mode transient. for transients occurring when the led is on, common- mode rejec tion (cmr l , since the output is in the low state) depends upon the amount of led current drive (i f ). for conditions where i f is close to the switching thresh - old (i th ), cmr l also depends on the extent which i lp and i ln balance each other. in other words, any condition where common-mode transients cause a momentary decrease in i f (i.e. when dv cm /dt>0 and |i fp | > |i fn |, referring to table 1) will cause common-mode failure for transients which are fast enough. likewise for common-mode transients which occur when the led is of (i.e. cmr h , since the output is high), if an imbalance between i lp and i ln results in a transient i f equal to or greater than the switching threshold of the optocoupler, the transient signal may cause the output to spike below 2 v (which consti tutes a cmr h failure). by using the recommended circuit in figure 20, good cmr can be achieved. (in the case of the -261n families, a minimum cmr of 15 kv/s is guaranteed using this cir - cuit.) the balanced i led -setting resistors help equalize i lp and i ln to reduce the amount by which i led is modulated from transient coupling through c la and c lc . cmr with other drive circuits cmr performance with drive circuits other than that shown in figure 20 may be enhanced by following these guidelines: 1. use of drive circuits where current is shunted from the led in the led of state (as shown in figures 22 and 23). this is benefcial for good cmr h . 2. use of i fh > 3.5 ma. this is good for high cmr l . using any one of the drive circuits in figures 22-24 with i f = 10 ma will result in a typical cmr of 8 kv/s for the hcpl-261n family, as long as the pc board layout prac - tices are followed. figure 22 shows a circuit which can be used with any totem-pole-output ttl/lsttl/hcmos logic gate. the bufer pnp transistor allows the circuit to be used with logic devices which have low current-sink - ing capability. it also helps maintain the driving-gate power-supply current at a constant level to minimize ground shifting for other devices connected to the in - put-supply ground. when using an open-collector ttl or open-drain cmos logic gate, the circuit in figure 23 may be used. when using a cmos gate to drive the optocoupler, the circuit shown in figure 24 may be used. the diode in parallel with the r led speeds the turn-of of the optocoupler led. figure 21. ac equivalent circuit for hcpl-261x. 350 1/2 r led v cc + 15 pf + v cm 8 7 6 1 3 shield 5 2 4 c la v o gnd 0.01 f 1/2 r led c lc i ln i lp ? 420 (max) 1 3 2 4 2n3906 (any pnp) v cc 74l504 (any ttl/cmos gate) hcpl-261x led
16 figure 24. cmos gate drive circuit for hcpl-261a/-261n families. figure 23. ttl open-collector/open drain gate drive circuit for hcpl-261a/-261n families. coup lers, diferences in propaga tion delays will cause the data to arrive at the outputs of the opto couplers at diferent times. if this diference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocou - plers. propagation delay skew is defned as the diference be - tween the minimum and maximum propaga tion delays, either t plh or t phl , for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and op - erating temperature). as illustrated in figure 25, if the in - puts of a group of optocouplers are switched either on or off at the same time, t psk is the difer ence between the shortest propagation delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 26 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through opto - couplers. table 1. efects of common mode pulse direction on transient i led if |i lp | < |i ln |, if |i lp | > |i ln |, led i f current led i f current if dv cm /dt is: then i lp flows: and i ln flows: is momentarily: is momentarily: positive (>0) away from led away from led increased decreased anode through c la cathode through c lc negative (<0) toward led toward led decreased increased anode through c la cathode through c lc propagation delay, pulse-width distortion and propagation delay skew propagation delay is a fgure of merit which describes how quickly a logic signal propagates through a sys - tem. the propaga tion delay from low to high (t plh ) is the amount of time required for an input signal to propa - gate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see figure 9). pulse-width distortion (pwd) results when t plh and t phl difer in value. pwd is defned as the diference between t plh and t phl and often determines the maximum data rate capability of a transmission system. pwd can be ex - pressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typical - ly, pwd on the order of 20-30% of the minimum pulse width is tolerable; the exact fgure depends on the par - ticular appli cation (rs232, rs422, t-1, etc.). propagation delay skew, t psk , is an important parameter to con sider in parallel data applications where synchro - nization of signals on parallel data lines is a con cern. if the parallel data is being sent through a group of opto - 820 1 3 2 4 v cc 74hc00 (or any open-collector/ open-drain logic gate) hcpl-261x led 750 1 3 2 4 v cc 74hc04 (or any totem-pole output logic gate) hcpl-261a/261n 1n4148 led
50% 1.5 v i f v o 50% i f v o t psk 1.5 v tphl tplh data t psk inputs clock data outputs clock t psk figure 25. illustration of propagation delay skew C t psk . figure 26. parallel data transmission example. the fgure shows data and clock signals at the inputs and outputs of the optocouplers. to obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. propagation delay skew repre sents the uncertainty of where an edge might be after being sent through an op - tocoupler. figure 26 shows that there will be uncertainty in both the data and the clock lines. it is important that these two areas of uncer tainty not overlap, otherwise the clock signal might arrive before all of the data out - puts have settled, or some of the data outputs may start for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. obsoletes av01-0561en av02-0391en - april 30, 2013 to change before the clock signal has arrived. from these considera tions, the absolute minimum pulse width that can be sent through optocouplers in a parallel applica - tion is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncer - tainty in the rest of the circuit does not cause a prob - lem. the t psk specifed optocouplers ofer the advantages of guaran teed specifcations for propaga tion delays, pulse- width distortion, and propagation delay skew over the recommended temperature, input current, and power supply ranges.

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